PCB Machine Jury

Why now

On September 4, EEBench used OpenAI’s demonstration of AI operating KiCad to ask how the reliability of model-generated circuits can be verified. ^S1 As of September 5, the discussion had 144 points and 84 comments on Hacker News, ranking tenth; a pre-fabrication review of AI-modified boards is therefore more likely to be on engineers' agenda.

Hardware engineers and small hardware teams using KiCad. The key moment comes after AI has changed a layout but before the design is submitted to a board fabricator. At that point, the files may look ready to manufacture, while rereading the whole design manually is time-consuming. Engineers need to confirm that the changes have not crossed fabrication limits or hidden high-speed, thermal, or footprint problems in local details.

Use KiCad projects as the only input format, parsing board files, rule files, and footprint references. Connect to the running editor through the KiCad IPC API and generate JSON DRC reports with `kicad-cli`. ^S2 First convert fabricator capability tables into version-controlled rule configurations. Initial checks focus on clearance, drill diameter, differential pairs, and thermal pads. Each conclusion outputs object coordinates, the rule expression, and input parameters. A signal or thermal finding that cannot produce a runnable check is downgraded to manual confirmation and cannot block release.

Early users are most likely to come through the KiCad plugin directory, open-source hardware repositories, and PCB-fabrication technical communities. Publish sample boards with deliberate defects so engineers can compare native DRC with incremental review results directly. Maintain public rule packs for common fabricators, using rule updates to drive return visits. Integrating with pull-request checks for open-source hardware projects would also put review reports into teams' existing workflows.

KiCad’s native DRC and manual reviewGoogle

KiCad already provides rule-driven DRC that can locate violating objects and export text or JSON reports. Engineers can also write custom rules by net, region, and footprint, and set global constraints from board-fabrication parameters. ^S2 It is well suited to checking rules that have already been expressed, but it does not proactively challenge the assumptions behind an AI-made change. Engineers must still judge the relationships among signal integrity, thermal behavior, and component data themselves. The opening is not to replace DRC, but to turn external constraints into executable rules. The product must also identify each rule’s source, applicable objects, and recheck result. Every finding should locate and run in KiCad, rather than creating another alert list that cannot be verified.

Cadence Allegro AI StudioGoogle

Cadence Allegro AI Studio already covers automated placement, constraint-driven routing, and multiphysics analysis. It brings signal, power, and thermal analysis into the design workflow and supports natural-language initiation of complex tasks. ^S3 These capabilities serve a full enterprise design and analysis stack with a strong existing automation loop. This product instead has an opening to accept KiCad projects generated or modified by external AI. It does not generate the layout again; it serves as an independent review layer. An initial version could offer a lighter pre-fabrication check centered on common four-layer boards and fabrication constraints. Its viability depends on whether findings are reproducible and whether teams can retain their existing EDA workflow.

Altium Designer rule checkingGoogle

Altium Designer is itself a rule-driven environment, with online and batch DRC. Its reports list enabled rules, violation counts, and specific violation details. ^S4 That already covers many routine checks used by mature teams and reduces the need for a separate review tool. What it does not directly address is how to review the risks introduced by a particular AI change. Teams still need to distinguish pre-existing issues, newly introduced issues, and accepted exceptions. The product could enter through before-and-after comparisons, targeted rechecks, and retained evidence. If it merely repeats clearance and trace-width checks, it will be hard to offer more value than native DRC.

Charge per review project, with a base fee covering one full check and several partial rechecks. A monthly team plan adds shared rule libraries, approval records, and private deployment options.

False positives would force engineers to review findings one by one and could bury serious issues in alerts. Fabricator capability tables often contain conditions, exceptions, and process options whose context can be lost when converted into rules. Signal-integrity and thermal judgments also depend on stackup, materials, and operating conditions that may not be present in the project files. A partial recheck that misses cross-region coupling could produce a false pass. Teams may also refuse to upload unreleased hardware designs. Without local operation, input-completeness checks, and explicit manual-confirmation states, it will be difficult to earn approvers' trust.